Computer Architecture MCQs - Chapter 26

Pipelining in Computer Architecture Multiple Choice Questions (MCQ) PDF - 10

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The MCQ: If the stages are perfectly balanced, then the time per instruction on the pipelined processor, is equal to; "Pipelining in Computer Architecture" App Download Android & iOS (Free) with answers time per instruction on unpipelined machine* no of piped stages, time per instruction on unpipelined machine/ no of piped stages, time per instruction on unpipelined machine + no of piped stages and time per instruction on unpipelined machine - no of piped stages for online computer science certification. Practice integrated circuits: power and energy quiz questions, download Apple Book (Free Sample) for software engineering online courses.

Pipelining in Computer Architecture Questions & Answers PDF Download: MCQ Quiz 10

MCQ 46: If the stages are perfectly balanced, then the time per instruction on the pipelined processor, is equal to

time per instruction on unpipelined machine/ no of piped stages
time per instruction on unpipelined machine* no of piped stages
time per instruction on unpipelined machine + no of piped stages
time per instruction on unpipelined machine - no of piped stages

MCQ 47: If the buffer is a queue with multiple instructions, it stalls when the queue

fills
gets empty
is half
none of above

MCQ 48: The instruction used in sequences to implement more complex instruction set is called a

resuming
nullifying
macroinstruction
microinstruction

MCQ 49: A processor with separate decode and register fetch stages will probably have a

canceling
nullifying
branch delay
branch table

MCQ 50: If some combination of instructions cannot be accommodated because of resource conflicts, the processor is said to have a

data hazard
structural hazard
pipeline hazard
stall

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Pipelining in Computer Architecture MCQs

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