Computer Architecture MCQs - Chapter 26

Pipelining in Computer Architecture Quiz Questions and Answers PDF - 11

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The Quiz: Assume that processor has a 1 ns clock cycle and that it uses 4 cycles for ALU operations branches and 5 cycles for memory and the relative frequencies of these operations are 40%, 20%, and 40%, respectively, then the average instruction execution time on the unpipelined processor is; "Pipelining in Computer Architecture" App Download iOS & Android (Free) with answers 4.2 ns, 4.4 ns, 3.4 ns and 3.2 ns for online degree programs. Study program translation quiz questions, download Amazon eBook (Free Sample) for computer science programs.

Pipelining in Computer Architecture Questions & Answers PDF Download: MCQ Quiz 11

MCQ 51: Assume that processor has a 1 ns clock cycle and that it uses 4 cycles for ALU operations branches and 5 cycles for memory and the relative frequencies of these operations are 40%, 20%, and 40%, respectively, then the average instruction execution time on the unpipelined processor is

A) 4.4 ns

B) 4.2 ns

C) 3.4 ns

D) 3.2 ns

MCQ 52: The instruction in different stages of the pipeline do not interfere with one another, the separation is done by

A) pipe stage

B) pipeline stacks

C) pipeline registers

D) processor cycle

MCQ 53: MIPS pipeline with the appropriate registers are also known as

A) pipeline latches

B) pipe stages

C) pipeline hits

D) pipeline buffers

MCQ 54: Pipeline interlock introduces a stall or bubble, just as in the

A) data hazard

B) control hazard

C) structural hazard

D) both a and b

MCQ 55: The time required between moving an instruction one step down the pipeline is a

A) clock cycle

B) hit rate

C) cycle rate

D) processor cycle

Computer Architecture Mock Tests

Networks, Storage and Peripherals MCQs

Embedded Systems MCQs

Interconnection Networks MCQs

Computer Memory Review MCQs

Instruction Level Parallelism MCQs

Instruction Set Principles MCQs

Request Level and Data Level Parallelism MCQs

Processor Datapath and Control MCQs

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