Digital Electronics MCQs - Chapter 9
Dynamic Logic Circuits Multiple Choice Questions (MCQs) PDF Download - 5
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Dynamic Logic Circuits Questions & Answers PDF Download: MCQ Quiz 5
MCQ 21: Cascading is not easily possible in
- TTL logic
- PTL logic
- CMOS logic
- Dynamic Logic
MCQ 22: In Dynamic logic when clock signal is low, PMOS turned ON and this phase is termed as
- precharge phase
- charge phase
- discharge phase
- evaluation phase
MCQ 23: As output of DOMINO CMOS gate is low, premature capacitance will
- charge
- discharge
- doesn't change
- remains constant
MCQ 24: For every 10° rise of temperature, current
- increase double
- increase triple
- decrease double
- decrease triple
MCQ 25: In Dynamic logic when clock signal is high, PMOS turned OFF and this phase is termed as
- precharge phase
- charge phase
- discharge phase
- evaluation phase
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Dynamic Logic Circuits MCQ Book Questions
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- High noise margin for dynamic logic circuits is equal to
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