Dynamic Logic Circuits Multiple Choice Questions 1 PDF Book Download

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MCQ on Dynamic Logic Circuits Test 1Quiz Book Download

MCQ: In Dynamic logic when clock signal is high, PMOS turned OFF and single NMOS at PDN will

  1. turned OFF
  2. turned ON
  3. doesn't change
  4. goes to breakdown region

B

MCQ: Low noise margin for dynamic logic circuit is equals to

  1. 5 V
  2. 3 V
  3. threshold voltage
  4. input voltage

C

MCQ: Output of DOMINO CMOS gate is low at beginning of

  1. precharge phase
  2. evaluation phase
  3. dynamic phase
  4. static phase

B

MCQ: High noise margin for dynamic logic circuits is equal to

  1. VDD-VTh
  2. 3 V
  3. threshold voltage
  4. input voltage

A

MCQ: Design of address decoders in memory chips can be done in

  1. TTL logic
  2. PTL logic
  3. DOMINO CMOS Logic
  4. CMOS logic

C