DOMINO CMOS Logic MCQs Quiz Online PDF Download

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MCQs on DOMINO CMOS Logic Quiz PDF Download

MCQ: Output of DOMINO CMOS gate is low at beginning of

  1. precharge phase
  2. evaluation phase
  3. dynamic phase
  4. static phase

B

MCQ: Design of address decoders in memory chips can be done in

  1. TTL logic
  2. PTL logic
  3. DOMINO CMOS Logic
  4. CMOS logic

C

MCQ: At rising edge of clock, output will make

  1. 0-1 transition
  2. 1-0 transition
  3. z-0 transition
  4. z-1 transition

A

MCQ: As output of DOMINO CMOS gate is low, premature capacitance will

  1. charge
  2. discharge
  3. doesn't change
  4. remains constant

C

MCQ: A form of dynamic logic that result in cascaded gates is termed as

  1. TTL logic
  2. PTL logic
  3. DOMINO CMOS Logic
  4. CMOS logic

C