Distributed Shared Memory and Coherence Quizzes Online MCQs PDF Download eBook
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Distributed Shared Memory and Coherence Questions and Answers PDF Download eBook
MCQ: When the calling procedure saving the registers which it wants to be preserved to access even after the call, is referred to as
- caller saving
- callee saving
- calls
- jumps
A
MCQ: If some combination of instructions cannot be accommodated because of resource conflicts, the processor is said to have a
- data hazard
- structural hazard
- pipeline hazard
- stall
B
MCQ: The node which has the memory location and the entry of directory of an address is
- home node
- guest node
- host node
- all above
A
MCQ: Architecture accessing memory only with the load instruction and the store instructions, is called
- load-store architecture
- load architecture
- store architecture
- 81x89
A
MCQ: Assume that processor has a 1 ns clock cycle and that it uses 4 cycles for ALU operations branches and 5 cycles for memory and the relative frequencies of these operations are 40%, 20%, and 40%, respectively, then the average instruction execution time on the unpipelined processor is
- 4.4 ns
- 4.2 ns
- 3.4 ns
- 3.2 ns
A