Computer Architecture Learning Notes and Technology Articles

Instruction Level Parallelism Multiple Choice Questions and Answers 1 PDF Download

Instruction level parallelism multiple choice questions, learn computer architecture online test prep 1 for CS degree, online courses. Practice exploiting ilp using multiple issue multiple choice questions (MCQs), instruction level parallelism quiz questions and answers. Learn exploiting ilp using multiple issue, dynamic scheduling algorithm, instruction level parallelism, advanced branch prediction, dynamic scheduling and data hazards career test prep for online advanced computer architecture courses distance learning.

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MCQ on Instruction Level Parallelism Test 1Quiz PDF Download

MCQ: If exploiting and finding parallelism, across branches require scheduling code, a substantially very difficult algorithm is

  1. Global scheduling
  2. Local scheduling
  3. Pre scheduling
  4. Post scheduling

A

MCQ: Having load before store in a running program order, then interchanging this order, results in a

  1. WAW hazards
  2. Destination registers
  3. WAR hazards
  4. Registers

C

MCQ: When instruction i and instruction j are tends to write same register or memory location, it is called

  1. Input dependence
  2. Output dependence
  3. Ideal pipeline
  4. Digital call

B

MCQ: Branch-selected entries in a (2,2) predictor, which is having a total of 8K-bits in prediction buffer are

  1. 1K
  2. 2K
  3. 3K
  4. 4K

A

MCQ: 10-bit history is used for allowing patterns of up to

  1. 10 branches
  2. 9 branches
  3. 8 branches
  4. 7 branches

A