Online Computer Science Degree Courses
Chapter 9: Computer Architecture Exam Tests
Computer Architecture MCQs - Chapter 9
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MCQ 26: The processor address's size determines the size of
MCQ 27: A direct-mapped cache having a size of N and has the miss rate the same as a two-way set-associative cache, of size
MCQ 28: The block placement strategy is if set-associative/direct-mapped, then this miss is called
MCQ 29: When Cycle per instruction is 1.0, data accesses are 50% of the total instructions, and the miss penalty is 25clock-cycles and the miss rate having 2%, then the computer would become faster by
MCQ 30: The address spaces are typically broken into the fixed-size blocks, called
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