Introduction to Pipelining MCQs Quiz Online PDF Download

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MCQs on Introduction to PipeliningQuiz PDF Download

MCQ: Pipeline overhead arises from combination of pipeline register delay and

  1. Hit rate
  2. Clock cycle
  3. Cycle rate
  4. Clock skew

D

MCQ: Each of clock cycles from previous section of execution, becomes a

  1. Pipe stage
  2. Previous stage
  3. Stall
  4. Processor cycle

A

MCQ: Decoding is done in parallel with reading registers, which is possiblebecause register specifiers are at a fixed location, stated technique is called a

  1. Variable-field decoding
  2. Fixed-field decoding
  3. Variable decoding
  4. fixed decoding

B

MCQ: Pipelining increases CPU instruction

  1. Size
  2. Through put
  3. Cycle rate
  4. Time

B

MCQ: Sum of contents of base register and sign-extended offset is used as a memory address, sum is known as

  1. ALU instructions
  2. Through put
  3. Effective address
  4. Load and store instructions

C