Design of Memory Hierarchies MCQs Test Online PDF Book Download

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MCQ on Design of Memory HierarchiesQuiz Book Download

MCQ: Cortex-A8 known as configurable core, which supports computer instruction set architecture of

  1. ARMv6
  2. ARMv7
  3. ARMv8
  4. ARMv9

B

MCQ: When cache having size 32k, block-size 64 and set associativity 4, will have cache index of

  1. 2^2
  2. 2^5
  3. 2^7
  4. 2^9

C

MCQ: Index of instruction cache is

  1. 2Index= Cache size- Block size ? Set associativity
  2. 2Index= Cache size/ Block size + Set associativity
  3. 2Index= Cache size+ Block size ? Set associativity
  4. 2Index= Cache size/ Block size ? Set associativity

D

MCQ: If L2 cache is missed and L3 cache is accessed. For a 4-core i7, which is having 8MB L3, index size will be

  1. 2^9
  2. 2^13
  3. 2^15
  4. 2^17

B

MCQ: Instruction miss which is serviced by main memory, has total latency, approximately of

  1. 35 processor cycles
  2. 40 processor cycles
  3. 42 processor cycles
  4. 45 processor cycles

A