Design of Memory Hierarchies Multiple Choice Questions (MCQ) PDF Download

MCQ 1: if ($s2 < $s3) $s1 = 1; else $s1 = 0 in assembly language can be written as

1. sll $s1,$s2,$s3
2. slt $s1,$s2,$s5
3. sll $s1,$s2,$s4
4. slt $s1,$s2,$s3

MCQ 2: To the server 90% of accesses are local, 9% are being outside the server but in the rack, and 1% are being outside the rack will be having average memory latency of

1. 12.09 microseconds
2. 12.09 nanoseconds
3. 11.09 microseconds
4. 11.09 nanoseconds

MCQ 3: A common optimization for reducing write stalls is a

1. write buffer
2. write-back
3. read stall
4. write stall

MCQ 4: The final stage of completion of an instruction, after which merely the result remains, is known

1. write result
2. read result
3. execute
4. commit

MCQ 5: Pipeline having stalls are required only a single time per vector instruction, instead of once per

1. vector register
2. vector element
3. chaining
4. line prediction