Design of Memory Hierarchies MCQs Quiz Online PDF eBook Download

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Practice design of memory hierarchies MCQ: Cortex-A8 known as configurable core, which supports computer instruction set architecture of, with choices armv6, armv7, armv8, and armv9 for online college courses. Practice merit scholarships assessment test, online learning design of memory hierarchies quiz questions for competitive exams in computer science major for computer science associate degree.

MCQs on Design of Memory Hierarchies PDF eBook Download

MCQ: Cortex-A8 known as configurable core, which supports the computer instruction set architecture of

  1. ARMv6
  2. ARMv7
  3. ARMv8
  4. ARMv9

B

MCQ: When cache having size 32k, block-size 64 and set the associativity 4, will have cache index of

  1. 2^2
  2. 2^5
  3. 2^7
  4. 2^9

C

MCQ: Index of instruction cache is

  1. 2Index= Cache size- Block size ? Set associativity
  2. 2Index= Cache size/ Block size + Set associativity
  3. 2Index= Cache size+ Block size ? Set associativity
  4. 2Index= Cache size/ Block size ? Set associativity

D

MCQ: If the L2 cache is missed and the L3 cache is accessed. For a 4-core i7, which is having 8MB L3, the index size will be

  1. 2^9
  2. 2^13
  3. 2^15
  4. 2^17

B

MCQ: Instruction miss which is serviced by the main memory, has total latency, approximately of

  1. 35 processor cycles
  2. 40 processor cycles
  3. 42 processor cycles
  4. 45 processor cycles

A