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Computer organization and architecture practice test MCQ: assume that hit-time is single clock cycle, independent of size of block, and then 16-byte block in a 4 kb cache will be having access-time of with options 6.027 clock cycles, 8.077 clock cycles, 7.027 clock cycles and 8.027 clock cycles for online certification exams, competitive tests for national and international scholarships for students. Free study guide is for online learning cache optimization techniques quiz with MCQs to practice test questions with answers.

MCQ: Assume that hit-time is single clock cycle, independent of size of block, and then 16-byte block in a 4 KB cache will be having access-time of

1. 6.027 clock cycles
2. 8.077 clock cycles
3. 7.027 clock cycles
4. 8.027 clock cycles

D

MCQ: A direct-mapped cache having a size of N and has miss rate same as a two-way set-associative cache, of size

1. N
2. N*2
3. N/2
4. N^2

C

MCQ: Rate of no of misses in a cache which is divided by whole number of memory-accesses, to cache, is known as

1. Local miss rate
2. Global miss rate
3. Hit rate
4. Miss rate

A

MCQ: Larger blocks increases conflict-misses and capacity-misses, whenever cache is

1. Great
2. Small
3. Large
4. Corrupt

B

MCQ: For Reducing Miss Rate, using Large blocks', given statement defines

1. First Optimization
2. Second Optimization
3. Third Optimization
4. Fourth Optimization

B