DOMINO CMOS Logic Multiple Choice Questions (MCQ) PDF Download

MCQ 1: Output of DOMINO CMOS gate is low at beginning of

1. precharge phase
2. evaluation phase
3. dynamic phase
4. static phase

MCQ 2: Design of address decoders in memory chips can be done in

1. TTL logic
2. PTL logic
3. DOMINO CMOS Logic
4. CMOS logic

MCQ 3: At rising edge of clock, output will make

1. 0-1 transition
2. 1-0 transition
3. z-0 transition
4. z-1 transition

MCQ 4: As output of DOMINO CMOS gate is low, premature capacitance will

1. charge
2. discharge
3. doesn't change
4. remains constant

MCQ 5: A form of dynamic logic that result in cascaded gates is termed as

1. TTL logic
2. PTL logic
3. DOMINO CMOS Logic
4. CMOS logic