Computer Hardware Procedures Quiz Questions and Answers 43 PDF Download

Practice computer hardware procedures quiz, computer architecture quiz 43 for online learning. Free computer architecture and organization MCQs questions and answers to practice computer hardware procedures MCQs with answers. Practice MCQs to test knowledge on computer hardware procedures, caches and cache types, virtual machines protection, multiplication calculations, 32 bits mips addressing worksheets.

Free computer hardware procedures worksheet has multiple choice quiz question as stack's segment that is used to have procedure's saved registers, is known as, answer key with choices as activation record, procedure frame, queue and both a and b problem solving to test study skills. For online learning, viva help and jobs' interview preparation tips, study computer language and instructions multiple choice questions based quiz question and answers.

Quiz on Computer Hardware Procedures Quiz PDF Download Worksheet 43

Computer Hardware Procedures Quiz

MCQ. The stack's segment that is used to have procedure's saved registers, is known as

  1. Activation record
  2. Procedure frame
  3. Queue
  4. both a and b

D

Caches and Cache Types Quiz

MCQ. Having a cache block of 4words, having one-word-wide bank of DRAMs and the miss penalty 65, then no of bytes transferred/bus-clock cycle for a single miss will be

  1. 0.2
  2. 0.25
  3. 0.75
  4. 1.5

B

Virtual Machines Protection Quiz

MCQ. The cache with special address translation, is referred to as a

  1. Translation look aside bus
  2. Translation look aside buffer
  3. Transistor look aside buffer
  4. Transistor look aside bus

B

Multiplication Calculations Quiz

MCQ. MIPS architecture provides a separate pair of 32-bit registers to contain the product of 64-bits called

  1. Hi
  2. Lo
  3. To
  4. both a and b

D

32 Bits MIPS Addressing Quiz

MCQ. The assembly language instruction corresponding to the machine code 00af8020hex is

  1. sub $s0,$a1,$t7
  2. add $s0,$a1,$t7
  3. mul $s0,$a1,$t7
  4. addi $s0,$a1,$t7

B